As the critical dimension of metal oxide semiconductor field effect transistor (MOSFET) devices continues to shrink, the short channel effect becomes more problematic. Fin field effect transistor (FinFET) devices have better control capability of gates than planar MOSFET devices to effectively suppress the short channel effect to facilitate a further size reduction of complementary metal oxide semiconductor (CMOS) devices.
Currently, in order to prevent punch-through between a source and a drain of a FinFET device, an anti-punch through implantation process needs to be performed to form an anti-punch through region below the source and the drain. However, a conventional anti-punch through implantation under the source region and the drain region may increase current leakage and parasitic capacitance, thereby reducing the device performance.